Altium

Design Rule Verification Report

Date:		09/03/2020
Time:		16:36:09
Elapsed Time:		00:00:02
Filename:		K:\Work\Z20X\processors\z380\electronics\PCB.PcbDoc

Warnings:		0
Rule Violations:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=0.24mm) (All),(All)	0
Clearance Constraint (Gap=0.35mm) ((IsRegion)),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Width Constraint (Min=0.2mm) (Max=0.5mm) (Preferred=0.2mm) (All)	0
Power Plane Connect Rule(Direct Connect )(Expansion=0.5mm) (Conductor Width=0.35mm) (Air Gap=0.35mm) (Entries=4) (All)	0
Hole Size Constraint (Min=0.025mm) (Max=2.5mm) (Disabled)(All)	0
Hole To Hole Clearance (Gap=0mm) (Disabled)(All),(All)	0
Minimum Solder Mask Sliver (Gap=-50mm) (Disabled)(All),(All)	0
Silk To Solder Mask (Clearance=-50mm) (Disabled)(IsPad),(All)	0
Silk to Silk (Clearance=-50mm) (Disabled)(All),(All)	0
Net Antennae (Tolerance=0mm) (Disabled)(All)	0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)	0
Silk primitive without silk layer	0
Total	0